Timeline Scheduling for Out-of-Core Ray Batching
(To appear) High Performance Graphics 2017
Abstract
We present a timeline based scheduling method for Monte Carlo ray
tracing of out-of-core models on distributed memory clusters. We abstract
different setups of various compute and memory devices into a graph-based
representation, and estimate the time for job execution and data transfer in a
simple timing model. Our scheduler allocates not only jobs to processors, but
also data transfers to memory channels. This approach allows us to control the I/O overload, which is the principal bottleneck in rendering massive-scale scenes. To manage
dependencies of data transfers and data intensive jobs, each job and data transfer is arranged
on the timeline with dependency relations.
Based on this model, our scheduler aims to increase data locality by allocating
a job that takes the least time to fetch required data on a given compute device.
This goal is achieved by optimizing the data transfer
path to maximize latency hiding effects. We have implemented a path tracer on
our framework and tested massive models up to 500 M triangles. Compared to prior state-of-the-art scheduling techniques, our renderer achieved higher horizontal scalability on flexible device configurations.
Contents
Paper (author preprint): Timeline Scheduling for Out-of-Core Ray Batching + Supplementary Report
HPG'17 talk slides
The code will be available soon!!
Dept. of Computer Science
KAIST
373-1 Guseong-dong, Yuseong-gu, Daejeon, 305-701
South Korea
sglabkaist dot gmail dot com
